The present invention relates generally to the field of electronics and in particular to a printed circuit board having power planes on the outermost layers.
The use of multi-layer printed circuit boards (PCB) is well known in the electronic arts. As circuit components simultaneously shrink in size, increase in complexity, and operate at higher frequencies, the resulting increased density, complexity and issues of electromagnetic compatibility have driven the need for printed circuit boards to provide an increasing number of layers with which to route electrical signals and power supply voltages to all components. A multi-layer PCB provides a plurality of electrically conductive layers separated by insulating dielectric layers. The conductive layers may comprise contiguous plane areas, or alternatively may comprise a complex pattern of point-to-point signal traces. The signal traces are arranged to provide the connectivity required among all of the components on the PCB, employing well known routing strategies, such as for example, primarily north-south traces on one layer, and primarily east-west traces on another layer. Both signal traces and power plane voltages may be propagated to other layers by vias, electrically conductive holes through one or more dielectric layers and possibly one or more conductive layers. Signal traces and power plane areas are routed away from vias passing through conductive layers that are not to be electrically connected at that level, as is well known in the art.
A typical “stack,” or arrangement of layers, for early multi-layer PCBs was to locate ground and/or power planes on internal conductive layers, and route signal traces on the outer PCB layers. This facilitated the interconnection of components with signal traces, requiring a minimum number of vias. As PCBs were populated with more complex components, such as microprocessors and Application Specific Integrated Circuits (ASIC), which often require multiple power supply voltage levels, additional internal power plane layers were added to the PCB stack.
With increasing operating frequency of many electrical circuits, the Electromagnetic Compatibility (EMC) of the PCB became a concern, as signal traces radiate electromagnetic energy at high frequencies, potentially causing interference with other electronic circuits. It was discovered that the use of contiguous power planes covering a significant area often improved signal quality and EMC performance. This is due to several factors, including the overall reduction of the loop area between the signal traces and their return signal paths, and the inherent decoupling provided by the distributed inter-plane capacitance. For example, a common stack for a 6-conductive-layer PCB is Signal-Power-Signal-Signal-Ground-Signal (often referred to as S-P-S-S-G-S). In this stack, the high-speed signals are routed on the two middle, or innermost, signal layers, between the power and ground plane layers. In this configuration, provided that the power plane is well decoupled to the ground plane, the power and ground planes together attenuate the electromagnetic fields radiated by those traces on the internal layers shielded by the power planes.
In circuits where most or all of the signal traces carry high frequency signals, it is known to “bury” all signal traces on internal conductive layers, and locate dedicated ground planes on the outer two PCB layers. Both the top and bottom conductive planes are formed in as large and contiguous an area as possible, both are connected to the ground reference voltage of the power supply, and the outer planes are interconnected to each other vertically through the use of vias generously located throughout the plane area. Positive power supply voltage levels may be distributed to components on one or more internal power plane layers, or alternatively as signal traces on one or more signal trace layers. On the outer layers, short traces from each component pin route the associated signal from each pin to a via, which connects to a signal trace located on an interior layer. To allow this routing, the area immediately adjacent the pins at each component position is clear of the ground plane, which fills the remainder of the outer layer with a contiguous ground plane. This PCB stack has been known to reduce electromagnetic emissions from the PCB by as much as 10 dB.
Although the use of outer ground planes provides a significant improvement in EMC performance of a PCB, there remain some situations where this implementation is not feasible or desirable. One example is the use of a component wherein the housing or a portion of the housing is maintained during operation at a voltage level other than ground, such as for example the collimator of a laser diode, or the tab of a TO-220 semiconductor package. In such cases, providing a ground plane on the outer layer would require that a large area of the ground plane be excluded from the vicinity of the relevant component. Signal traces routed to this component would no longer have the ground plane in close proximity, resulting in greater emissions. Alternatively, if the outer ground plane were placed closer to the part to reduce emissions, there is an increased risk of a short circuit between the component housing and ground.
It is desirable, therefore, to provide positive or negative voltage level power planes—rather than a ground plane—as the outermost layers in a multi-layer PCB stack. U.S. Pat. No. 6,288,906 discloses a printed circuit board having power plane layers at the outermost layer positions. The outer power planes of the '906 patent, however, are connected to different positive supply voltages. As described above, it is known that generously interconnecting the two outer ground plane layers by vias increases the EMC performance of the PCB. The direct connection of outer power planes by vias is impossible when the planes are maintained at different voltages.